1. Field of the Invention
This invention relates to a data processing system having an external instruction set and an internal instruction set, for example to such systems having instruction cache memories, particularly using a memory structure combined with a software or hardware translator to decouple the externally visible instruction sets of a processor from the internally implemented instruction sets.
2. Description of the Prior Art
It is known from U.S. Pat. No. 6,332,215 to provide a system in which external Java bytecodes are translated into internal native processor instructions by instruction translation hardware.
It is known from the trace cache mechanisms of the Pentium IV processors produced by Intel Corporation to store data representing the previous execution path through a set of basic blocks of computer code such that a speculative trace may be easily fetched without having to individually fetch its constituent basic blocks as a measure to increase processing speed within a deeply pipelined system. The trace information is stored in a conventional cache using fixed-sized lines with pointers in the tags to specify the speculative trace structure. As will be seen, the present invention is not built on top of a traditional cache structure; it implements a temporal cache consisting of variable sized blocks on top of a standard RAM structure, which facilitates greater space efficiency and faster operation.
It is known in the microprocessors produced by Transmeta to provide a system in which software is used to translate from a non-native instruction set into a native instruction set and then manage that translation for execution upon the processor.
It is known to provide microprocessors which support multiple external instruction sets. An example of these are ARM architecture microprocessors which currently support three external instruction sets, namely the ARM, Thumb and Java instruction sets. Whilst it is desirable to be able to extend the number of different instruction sets supported by a particular microprocessor, a multiplicity of instruction sets tends to introduce extra complexity in the decoder, which in turn can adversely impact the performance and power consumption of the processor.